FIG. 1 depicts a schematic diagram of a circuit in the prior art that is often used for trimming the peak-to-peak voltage of a binary signal. For the purposes of this specification, the peak-to-peak voltage of a binary signal is defined as the difference between the voltage of the signal when it represents a binary "1" minus the voltage of the signal when it represents a binary "0." For example, when standard TTL circuitry is used and V.sub.cc is 5 volts, a binary "1" is typically represented by 4.0 volts, a binary "0" is typically represented by 0.3 volts, and, therefore, the peak-to-peak voltage of that signal is 3.7 volts.
When the binary signal is used as the input to an analog circuit (e.g., a voltage-controlled oscillator that uses the binary signal to modulate a carrier as in a frequency-shift keying modulation scheme), it is often necessary that the peak-to-peak voltage at the input to the analog circuit be precisely tuned, and that the peak-to-peak voltage be centered around the linear region of operation of the analog circuit (usually about Vcc/2).
The schematic in FIG. 1 comprises: signal source 101, trimming potentiometer 103, capacitor 105 and signal destination 107. Signal source 101 has a tri-state output and signal destination 107 is an active analog circuit such as a voltage-controlled oscillator.
When signal source 101 outputs a signal, trimming potentiometer 103 can be adjusted to affect the peak-to-peak voltage of the binary signal entering signal destination 107. When signal source 101 enters the high-impedance state, no current flows on lead 102 and any residual voltage on lead 102 falls to zero. Analogously, no current flows on lead 104 and any residual voltage on lead 104 falls to zero. When the voltage on lead 104 falls to zero, a current flows on lead 106 from the active circuitry within signal destination 107 and typically charges capacitor 105 to a voltage that is centered around the linear region of operation of the analog circuit (usually about Vcc/2). This charging of capacitor 105 is disadvantageous because the voltage on lead 106 is the sum of the voltage across capacitor 105 plus the voltage on lead 104, and, therefore, when signal source 101 exits the high-impedance state, the voltage on lead 106 can rise above the operating range of signal destination 107.
For example, FIG. 2 depicts a graph of the voltage on lead 102, which represents an illustrative binary signal from signal source 101. For the first four time periods shown, a time-varying binary signal is output by signal source 101. At t=4, signal source 101 enters the high-impedance state and the voltage on lead 102 falls from its prior value towards zero. At t=7, signal source 101 exits the high-impedance state and again outputs a time-varying binary signal.
FIG. 3 depicts a graph of the voltage on lead 106 that is caused by the binary signal in FIG. 2. For the first four time periods, the voltage on lead 106 follows the voltage on lead 102. When at t=4 signal source 101 enters the high-impedance state the voltage on lead 106 tends towards the voltage in the center of the region of linearity of signal destination 109. When at t=7 signal source 101 exits the high-impedance state the voltage on lead 106 immediately becomes the sum of the voltage on lead 104 plus the voltage across capacitor 106. This causes the voltage on lead 106 to be higher than desired until the time that capacitor 105 discharges and equilibrium is restored (at about t=17). When the voltage on lead 106 is higher than the expected operating range, those bits output by signal source 101 will be misinterpreted by signal destination 107.
In summary, the circuit depicted in FIG. 1 has three principal disadvantages. The first disadvantage is that trimming potentiometer 103 must be manually and mechanically adjusted. This necessitates the need for human intervention and opens the possibility for human error. Furthermore, because trimming potentiometer 103 is a mechanical device the possibility exists that it will untune from vibration and/or thermal cycling.
The second disadvantage of this circuit is that the process of adjusting trimming potentiometer 103 affects both the peak-to-peak voltage on lead 106 and the voltage of symmetry (i.e., the DC frequency component) of the signal, which can make tuning the circuit difficult or impossible, because it provides only one degree of freedom to affect two independent parameters. The third disadvantage of this circuit is that the first few bits output by signal source 101 are misinterpreted after signal source 101 exits the high-impedance state.
Therefore, the need exists for a circuit that can be tuned without human intervention, that allows the peak-to-peak voltage to be tuned independently of the voltage of symmetry and that does not cause bits to be misinterpreted after the signal source exits the high-impedance state.